ARM Profile Overview
ARM (Advanced RISC Machines) is a well-known company in the microprocessor industry, designing a large number of high-performance, inexpensive, and energy-efficient RISC processors, related technologies, and software. The technology is characterized by high performance, low cost and energy saving. It is suitable for a wide range of fields, such as embedded control, consumer/educational multimedia, DSP and mobile applications.
Introduction to ARM UK
Country: United Kingdom (Europe) ARM Industry: Electronics Semiconductors Microprocessors Smartphones Headquarters: Cambridge, United Kingdom CEO: Warren Easter Competitors: Intel Market share 90% market share of cell phone processors 30% market share of netbook processors
Cell phones with ARM processors
Nokia Europe
Nokia N86 Nokia N97 Nokia N8 Nokia N96 Nokia N95 Nokia N900 Nokia N81 Nokia N85 Nokia X6 Nokia E72 Nokia E71 Nokia E66 Nokia E63 Nokia E52 Nokia E5 Nokia 5530XM Nokia 5800XM Nokia 5320XM Nokia 5730XM Nokia 5230 etc. 5230, etc.
Motorola USA
Motorola XT800 Motorola XT702 Motorola XT701 Motorola ME600 Motorola ME501 Motorola ME500 Motorola Milestone Motorola RAZR V8 Motorola VE66 Motorola A1200E Motorola A1210 Motorola A1600 Motorola A1800 Motorola A1890 Motorola U9 Motorola A810 Motorola ROKR EM30 Motorola EM35 Motorola ROKR E6
Sony Ericsson
Sony Ericsson X1 Sony Ericsson X2 Sony Ericsson M1i Sony Ericsson X10 Sony Ericsson Satio Sony Ericsson U8i, etc.
Apple
iPhone iPhone 3GS
Samsung Korea
Samsung i8910 Samsung i8510, etc.
ARM
ARM licenses its technology to many of the world's leading semiconductor, software, and OEM vendors, each of whom receives a unique set of ARM-related technologies and services. Utilizing this partnership, ARM quickly became the creator of many global RISC standards. Currently, a total of 30 semiconductor companies have signed hardware technology license agreements with ARM, including such large companies as Intel, IBM, LG Semiconductor, NEC, Sony, Philips and Nationwide Semiconductor. As for software system partners, they include a series of well-known companies such as Microsoft, Sunrise and MRI etc. The ARM architecture is the first RISC microprocessor designed for the low-budget market. ARM is the abbreviation of Advanced RISC Machines, which can be regarded as either the name of a company or a generic term for a class of microprocessors, or the name of a technology. On April 26, 1985, the first ARM prototype was born at Acorn Computers Ltd. in Cambridge, England, and manufactured by VLSI Technologies in San Jose, California, U.S.A. In the late 1980s, ARM was quickly developed into Acorn's desktop products, forming the basis of computer education in the U.K. In 1990, Advanced RISC Machines Limited (later shortened to Advanced RISC Machines Limited) was established. Machines Limited (later shortened to ARM Limited, ARM Corporation). 1990s, ARM 32-bit embedded RISC (Reduced lnstruction Set Computer) processor expanded to the world, occupying the low-power, low-cost and high-performance embedded systems applications in the field of ARM neither produces nor sells chips, it only sells chip technology licenses.
ARM learning and development need to learn what software
Summarize the most important of the following 1 ADS debugging with the exact ADS + AXD. ADS contains AXD. original use SDT later ARM company stopped support for SDT, changed to support ADS, or use ADS it. Some people's programs are still released in SDT version, but basically you can find the corresponding ADS, newcomers should not be confused here.ADS is the compiler, AXD is the debugger. Compiled into AXF and then debugged in the ARM RAM.2 FLASHPGM FLASH burning software. AXF debugging in RAM, power down will be gone, convenient program modification. Debugging a good program and then down to FLASH, power on the direct run. There are many similar software, what FLUTED, FLSHP are, but FLASHPGM is the best, if someone is still asking FLASH does not support BIN format files will have to look at me to write the use of FLASHPGM. 3 BANYANT debugging agent (I do not know the name of the right to get up such a difficult to remember, I usually call it "! half a sheep" because I know it just ate a roasted lamb in the last few days) debugging agent is to use it to help you use a simpler JTAG (cheap ah) to achieve the original 1K to sell most of the functions of the JTAG emulator. JTAG debugging principle to see another one of my notes. Simple to understand him as you do your own JTAG driver on the line. Debugging agent there are many kinds, what H-JTAG, ARM7 (do not know what to call, just remember the executable file called ARM7.EXE) are, BANYANT better. It should be noted that each debugging agent installation method is simple but different, you need to read the instructions. And AXD debugging before they all have to run. Save money, don't be afraid of trouble.4 ARM-ELF-TOOLS tool chain Inside is UCLINUX development with tools such as ARM-ELF-GCC only class. Tool chain is a lot of tools packaged together to facilitate your development of things. Specific installation method to see my other notes. In addition, if you develop LINUX should use ARM-LINUX-TOOLS, not the same, not universal. 5 U-BOOT big name BOOTLOADER generation tool, similar seems to have VIVI (name is very ambiguous ~ ~) generated BOOTLOADER burned into FLASH, then you can use BOOTLOADER to download Burning other The BOOTLOADER is like a BIOS on a computer, of course, UCOS does not use this, I do not know what to use :) The latest version is 1.1.4 Specific methods of use see my other notes. 6 UCLINUX package UCLINUX source code package, needless to say, right? It is recommended that you use the ready-made first experience, and then compile and cut their own. Because the editing of a separate UCLINUX is technically simple, but the aspects involved are still relatively broad.7 VMWARE The old virtual machine software, virtualized on a machine to install a machine LINUX (used on the PC), saving you from switching back and forth. Remember to install VMWARE-TOOLS. 8 source insight code editing tool linux using kscope
About ARM
ARM was founded in 1991 in Cambridge, UK, to sell licenses for chip design technology. Currently, microprocessors using ARM's intellectual property (IP) cores, commonly referred to as ARM microprocessors, have spread across a wide range of product markets such as industrial control, consumer electronics, communications systems, networking systems, wireless systems, etc. ARM technology-based microprocessor applications account for more than 75% of the market for 32-bit RISC microprocessors, and ARM technology is gradually penetrating into all aspects of our lives. ARM is a company specializing in the design and development of RISC technology-based chips, as an intellectual property supplier, not directly engaged in the production of chips, by transferring the design license by the partner companies to produce a variety of unique chips, the world's major semiconductor manufacturers to buy their ARM microprocessor cores from ARM, according to their different applications, adding appropriate peripheral circuits, thus forming its own According to their different application areas, they add appropriate peripheral circuits to form their own ARM microprocessor chips to enter the market. Currently, dozens of large semiconductor companies around the world use ARM's license, which not only makes ARM technology get more third-party tools, manufacturing, and software support, but also reduces the cost of the whole system, making it easier for products to enter the market and be accepted by consumers, and is more competitive. the three main features of the ARM processor are: low power consumption and strong functionality, 16-bit/32-bit dual instruction set, and a large number of partners. The strength of ARM's commodity model is that it has more than 100 partners around the world. ARM is a design company and does not produce chips itself. ARM is a design company and does not produce chips itself, but uses a transfer license system where partners produce chips. Expansions to the current ARM architecture include: the Thumb 16-bit instruction set for improved code density; an instruction set for arithmetic operations for DSP DSP applications; and Jazeller to allow direct execution of Java bytecode.The ARM family of processors provides solutions for: open platforms for wireless, consumer electronics, and graphics applications; embedded real-time systems for storage, automation, industrial, and networking applications; smart cards and SIM cards; and embedded real-time systems for smart cards and SIM cards. real-time systems; and smart card and SIM card security applications. the ARM processor itself is a 32-bit design, but also comes with a 16-bit instruction set. Generally speaking memory savings of up to 35% over equivalent 32-bit code are achieved, yet all the advantages of 32-bit systems are retained.ARM's Jazelle technology enables Java acceleration to achieve much higher performance than software-based Java Virtual Machines (JVMs), and power consumption is reduced by up to 80% compared to equivalent non-Java-accelerated cores.The addition of a DSP instruction set to the CPU's functionality provides enhanced 16- and The addition of the DSP instruction set to the CPU functionality provides enhanced 16-bit and 32-bit arithmetic capabilities for increased performance and flexibility. ARM also offers two leading-edge features to assist in the debugging of highly-integrated SoC devices with deeply embedded processors: the Embedded ICE-RT Logic and Embedded Trace Macrocore (ETMS) families.
Design Documentation
The design file is a lean and fast design, circuitized but not microcoded, like the 8-bit 6502 processor used in the early days of the Acorn microcomputer.The ARM architecture includes the following RISC features: read/store Architecture does not support address-unaligned memory accesses (which are now supported by the ARMv6 kernel) Orthogonal instruction set (any-access instructions access data in an arbitrary way) Large 16 × 32-bit register arrays (register file) Fixed 32 bits opcode length to reduce the cost of decoding. Orthogonal instruction set (large 16 × 32-bit register file) Fixed 32 bits opcode length to reduce the cost of encoding and reduce the burden of decoding and pipelining. Most of them are executed in one CPU cycle. To complement this simplicity, some special features have been added compared to contemporaneous processors such as the Intel 80286 and the Motorola 68020: most instructions can be executed conditionally, reducing the load at branch time and compensating for the lack of a branch predictor. Arithmetic instructions only change the condition code on demand. The 32-bit barrel shifter can be used to perform most arithmetic instructions and addressing calculations without loss of performance. Storages have a fun addition to the ARM design, which is the use of a 4-bit conditional code in front of each instruction, indicating whether the execution of each instruction is conditional This greatly reduces the number of bits of code used in memory access instructions, in other words, it avoids branching instructions in small narratives such as if. There is a standard example citing Euclid's greatest common divisor algorithm: in the C programming language, the loop is: int gcd (int i, int j) { while (i ! = j) if (i > j) i -= j; else j -= i; return i;} In ARM assembly language, the loop is: loop CMP Ri, Rj ; set condition to "NE" (not equal to) if (i ! = j) ; "GT" (greater than) if (i > j), ; or "LT" (less than) if (i < j) SUBGT Ri, Ri, Rj ; if "GT" (greater than), i = i-j; SUBLT Rj, Rj, Ri ; if "LT" (less than), j = j-i; BNE loop ; if "NE" (unequal to), then continue to loop which bypasses the gap between the then This avoids branching between then and else clauses. Another feature of the instruction set is the ability to combine functions such as shift and rotate into "data processing" type instructions (arithmetic, logic, and storageshift), so for example, a C statement a += (j << 2); can be simplified under ARM to a word and cycle instruction ADD Ra, Ra, Rj, LSL Ra, Rj, LSL #2 The result is that a typical ARM program can be made much tighter without the need for frequent memory accesses, and the pipeline can be used more efficiently. Even when ARM executes at speeds generally considered slow, it still performs well compared to more complex CPU designs.The ARM processor also has a number of features not commonly found in other RISC architectures, such as PC-relative addressing (indeed, on ARM, the PC is one of 16 registers) and pre-incremental or post-incremental addressing modes. Another caveat is that the ARM processor will continue to increase its instruction set over time. Some early ARM processors (earlier than the ARM7TDMI), for example, may not have had instructions that could read two bytes, so it would not be strictly possible to generate code for these processors that could handle data types such as the "volatile short" used in C objects. The ARM7, and most earlier designs, had a three-phase pipeline: instruction extraction, instruction storage, and addressing. ARM7 and most older designs have a three-stage pipeline: extract instructions, decode them, and execute them. Higher performance designs, such as ARM9, have a five-stage pipeline. Additional ways to improve performance include a faster adder and a wider range of branch prediction logic lines. The architecture uses "coprocessors" to provide a non-intrusive way to extend the instruction set, which can be addressed through software instructions such as MCR, MRC, MRRC and MCRR. The coprocessor space is logically divided into 16 coprocessors, numbered from 0 to 15, with coprocessor 15 (CP15) reserved for certain common control functions, such as the use of cache and memory management unit operations (if included in the processor). In ARM-architecture machines, peripheral devices are connected to the processor, usually through physical registers of the device corresponding to ARM's memory space, coprocessor space, or to another device (e.g., a bus) that is sequentially connected to the processor. Co-processors have lower access latency, so some peripherals (e.g. XScale interrupt controllers) are designed to be accessed in different ways (through memory and co-processors).
Thumb
Newer ARM processors have a 16-bit instruction mode called Thumb, which may have something to do with the fact that each conditionally executed instruction uses four bits. In Thumb mode, smaller opcodes have less functionality. For example, only branches can be conditional, and many opcodes do not have access to all CPU registers. However, shorter opcodes provide overall better code density (note: meaning the amount of space the program code occupies in memory), even if some operations require more instructions. Especially in situations where memory ports or bus widths are limited to less than 32, shorter Thumb opcodes make more efficient use of limited memory bandwidth, thus providing better performance than 32-bit code. Typical embedded hardware only has a small 32-bit datapath addressing range and other narrower 16 bits addressing (e.g. Game Boy Advance). In such cases, it is often feasible to compile Thumb code and self-optimize some of the CPU-related program areas that use the (non-Thumb) 32-bit instruction set, so that they can fit into the limited 32-bit bus width of memory. The first processor with Thumb technology was the ARM7TDMI, and all ARM9 and later families, including XScale incorporate Thumb technology.
Jazelle
ARM has also developed a technology, Jazelle DBX (Direct Bytecode eXecution), which allows them to accelerate the execution of Java bytecode on certain architectures of hardware, just like other execution modes, when calling special software that cannot support bytecodes. bytecodes when calling special software that does not support bytecodes. It is interoperable between existing ARM and Thumb modes. The first processor to feature Jazelle technology was the ARM926EJ-S: Jazelle is denoted by the letter ''J'' in the CPU name. It is used to enable cell phone manufacturers to accelerate the execution of Java ME games and applications, which has led to the continued development of this technology.
Thumb-2
Thumb-2 technology first appeared on the ARM1156 core and was released in 2003.Thumb-2 expands the limited 16-bit Thumb instruction set with additional 32-bit instructions to make the instruction set more widely available. The intended goal of Thumb-2 is to achieve a coding density close to that of Thumb, but with performance close to that of the ARM instruction set in 32-bit memory.Thumb-2 has so far derived a variety of instructions from the ARM and Thumb instruction sets, including bit-field operations, table branches, and conditional execution. conditional execution.
Thumb Execution Environment (ThumbEE)
ThumbEE, also known as Thumb-2EE, is the industry's version of the Jazelle RCT technology, published in 2005 and first seen in the Cortex-A8 processor. Thumb-2EE is designed for languages such as Limbo, Java, C#, Perl, and Python, and allows on-the-fly compilers to output more code. New features provided by ThumbEE include automatic checking for invalid indicators each time an instruction is accessed, an instruction that performs array range checking, and the ability to branch to handlers, which contain a small portion of the frequently-called code that is often used for higher-order language functions, such as Memory allocation for a new object.
Advanced SIMD (NEON)
The Advanced SIMD extension set, known in the industry as NEON technology, is a combination of 64 and 128 bit SIMD (Single Instruction Multiple Data) instruction sets with standardized acceleration capabilities for multimedia and signal processing programs. NEON can perform MP3 audio decoding on a 10 MHz CPU and GSM AMR (Adaptive Multi-Rate) speech coding up to 13 MHz. NEON has an extensive instruction set, its own register array, and execution-independent hardware. NEON supports 8-, 16-, 32-, and 64-bit integer and single-precision floating-point data and performs the speech/video portion of graphics and game processing in SIMD. SIMD is a decisive element in the Vector Hyperprocessor, which has simultaneous multiprocessing capabilities. In NEON technology, SIMD supports up to 16 simultaneous operations.
VFP
VFP is a derivative technology of the ARM architecture for co-processors. It provides low-cost single- and double-precision floating-point computing and is fully compatible with the ANSI/IEEE Std 754-1985 binary floating-point arithmetic standard.VFP provides the majority of floating-point applications, such as PDAs, smartphones, voice compression and decompression, 3D graphics and digital audio, printers, set-top boxes, and automotive applications.The VFP architecture also supports SIMD nbsp;SIMD (Single Instruction Multiple Data) parallelized short vector instruction execution. This is very helpful in applications such as image and signal processing to reduce code size and increase output efficiency. Other visible floating-point, or SIMD, co-processors in ARM-based processors include FPA, FPE, iwMMXt. They provide VFP-like functionality but are not compatible at the opcode level.
Security Extension (TrustZone)
TrustZone(TM) technology is found in the ARMv6KZ and later application core architectures. It provides a low-cost solution for adding a proprietary security core to a System-on-Chip (SoC) with hardware-constructed access control to support two virtual processors. This approach allows the application program core to switch between two states (often renamed worlds to avoid confusion with the names of other functional domains), and in this architecture avoids information leakage from the more trusted core domain to the less secure domain. This switching between core domains is usually completely orthogonal to the rest of the processor, so that each domain can operate independently but still use the same core. Memory and peripheral devices can therefore know which domain the core is currently operating in, and can provide access to the secrets and code of the device in this way. Typical TrustZone technology applications are to be able to fully execute an operating system in an insecure environment, and to have less secure code in a trusted environment.
ARM Licensees
ARM does not manufacture or sell CPUs based on its own designs, but rather licenses its processor architecture to interested parties, under a variety of licensing terms, including items such as price and distributability. For licensees, ARM provides an integrated hardware narrative for the ARM core, including complete software development tools (compiler, debugger, SDK), and the right to sell silicon chips with ARM CPUs inside. For fabless licensees wishing to integrate the ARM core into their self-developed chip designs, the goal is usually to obtain a production-ready IP Core certification. For these customers, ARM releases gate circuit diagrams for selected ARM cores, along with abstract simulation models and test programs to assist with design integration and verification. More customers, including Integrated Device Manufacturers (IDMs) and foundries, are choosing the synthesizable RTL (Register Transfer Level, e.g., Verilog) form factor to acquire the intellectual property (IP) of the processor. With synthesizable RTL, customers have the ability to optimize and enhance their architectures. This approach allows designers to accomplish additional design goals (e.g., high oscillator frequency, low power dissipation, instruction set extensions, etc.) without being constrained by an immutable circuit diagram. While ARM does not grant a licensee the right to re-sell the ARM architecture itself, a licensee can sell as many products as they like (e.g., silicon components, evaluation boards, complete systems, etc.). Commercial foundries are a special case because not only do they grant the right to sell finished silicon containing the ARM core, but for other customers, they usually reserve the right to reproduce the ARM core as well. Like most IP sellers, ARM determines the price of IP based on value in use. Architecturally, lower-energy ARM cores have lower license fees than higher-energy cores. In silicon terms, an integrable core is more expensive than a hardware macro (black box) core. To further complicate the price point, commercial foundries with ARM licenses, such as Samsung in Korea and Fujitsu in Japan, can offer lower license prices to their fab customers. Through the fab's own design technology, customers can obtain ARM cores at lower or no ARM upfront license fees. Fujitsu/Samsung charge two to three times more per wafer than specialized semiconductor foundries (such as TSMC and UMC) that do not have their own design technology. For small- to medium-volume applications, fabs with design departments offer lower overall prices (through license fee subsidies). For volume production, dedicated foundries are also a better option as long-term cost reductions can be achieved through lower wafer prices, reducing ARM's NRE costs. Many semiconductor companies hold ARM licenses: Atmel, Broadcom, Cirrus Logic, Freescale (which became independent from Motorola in 2004), Fujitsu, Intel (mediated through a lawsuit with Digital), IBM, Infineon Technologies, Nintendo, NXP Semiconductors (which became independent from Philips in 2006), OKI Electric Industries, Samsung, and NXP Semiconductors. ), OKI Electric Industries, Samsung Electronics, Sharp, STMicroelectronics, Texas Instruments and VLSI and many of these companies have various forms of ARM license. Although ARM's license program is covered by confidentiality contracts, in the intellectual property industry, ARM is widely known as one of the most expensive CPU cores. A single customer product containing a basic ARM core may require a license fee of up to $200,000 per license. ARM (Asynchronous Resbonse Mode) Asynchronous Responses Mode ARM (Asynchronous Responses Mode) is also a type of unbalanced data link operation, and unlike NRM, the transmission process under ARM is initiated by the slave. process is initiated by the slave. One or a group of frames sent by the slave to the master may contain information, or may be frames sent for control purposes only. In this mode of operation, the slave controls the timeout and retransmission. This method is essential for multi-station links that use polling.